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gnucap:manual:examples:spice_to_verilog [2023/04/21 08:18] felixs created |
gnucap:manual:examples:spice_to_verilog [2024/04/18 17:17] (current) felixs primitive library update |
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| == circuit in verilog, testbench in spice == | == circuit in verilog, testbench in spice == | ||
| - | The "spice" command is a shorthand for ''option lang=spice'' it passes control of the input to the spice language plugin. | + | The "spice" command is a shorthand for ''option lang=spice''. it passes control of the input to the spice language plugin. |
| - | NB: language plugins are user defined, so here you can use your own Spice flavour if so required.) | + | (NB: language plugins are user defined, so here you can use your own Spice flavour if so required.) |
| <code> | <code> | ||
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| == circuit in verilog, testbench cleaned up == | == circuit in verilog, testbench cleaned up == | ||
| - | While SPICE is build on letter to device mapping (V means voltage source) and some implmentation defined modelling extensions (here: sin), Verilog-AMS defines a list of standard primitives that ought to behave identical across platforms. | + | While SPICE is built on letter to device mapping (V means voltage source) and some implmentation defined modelling extensions (here: sin), Verilog-AMS defines a list of standard primitives that ought to behave identical across platforms. |
| - | For example, ''vsin'' provides a voltage source controlled by a time dependent sine wave with ports ''p'' and ''n'', and the expected parameters (see LRM). | + | For example, ''vsine'' provides a voltage source controlled by a time dependent sine wave with ports ''p'' and ''n'', and the expected parameters (see LRM). |
| This allows us to refactor the test bench into a portable presentation. | This allows us to refactor the test bench into a portable presentation. | ||
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| == native primitives == | == native primitives == | ||
| - | In the above section, the instanciation of ''vsine'' pulls in the spice wrapper subcircuit. In the future, such devices will be compiled directly from behavioural models, and provided as a package. In this case, an implementation will look strucutrally like this. | + | In the above section, the instanciation of ''vsine'' pulls in the spice wrapper subcircuit. Such devices can as well be compiled directly from portable behavioural code. In this case, the code will look approximately like this. |
| <code> | <code> | ||
| `include "disciplines.h" | `include "disciplines.h" | ||
| - | module vsin(p, n); | + | module vsine(p, n); |
| parameter ampl; | parameter ampl; | ||
| parameter freq; | parameter freq; | ||
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| </code> | </code> | ||
| - | And its instanciation will require a "model compiler"; or "generator". | + | A (growing) primitive library is now contained in the modelgen-verilog package. Precompiled modules are installed with it; load all with ''load vams'', or load individually, e.g. ''load vams/vsine.so''. |