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gnucap:manual:examples:spice_to_verilog [2023/04/21 08:18]
felixs created
gnucap:manual:examples:spice_to_verilog [2023/04/21 16:22] (current)
felixs typo
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 == circuit in verilog, testbench in spice == == circuit in verilog, testbench in spice ==
  
-The "spice" command is a shorthand for ''option lang=spice'' it passes control of the input to the spice language plugin. +The "spice" command is a shorthand for ''option lang=spice''it passes control of the input to the spice language plugin. 
-NB: language plugins are user defined, so here you can use your own Spice flavour if so required.)+(NB: language plugins are user defined, so here you can use your own Spice flavour if so required.)
  
 <code> <code>
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 == circuit in verilog, testbench cleaned up == == circuit in verilog, testbench cleaned up ==
  
-While SPICE is build on letter to device mapping (V means voltage source) and some implmentation defined modelling extensions (here: sin), Verilog-AMS defines a list of standard primitives that ought to behave identical across platforms.+While SPICE is built on letter to device mapping (V means voltage source) and some implmentation defined modelling extensions (here: sin), Verilog-AMS defines a list of standard primitives that ought to behave identical across platforms.
  
 For example, ''vsin'' provides a voltage source controlled by a time dependent sine wave with ports ''p'' and ''n'', and the expected parameters (see LRM). For example, ''vsin'' provides a voltage source controlled by a time dependent sine wave with ports ''p'' and ''n'', and the expected parameters (see LRM).
gnucap/manual/examples/spice_to_verilog.1682083131.txt.gz · Last modified: 2023/04/21 08:18 by felixs
 
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