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gnucap:manual:languages:verilog [2023/01/05 16:33] felixs paramset new/WIP stub |
gnucap:manual:languages:verilog [2024/01/30 11:47] (current) felixs lang_verilog now in mgsim |
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| All components have the same syntax: | All components have the same syntax: | ||
| - | type #(arguments) label (port list) ; | + | type #(parameters) label (port list) ; |
| * **Type** : The type of component. If there is a "paramset" statement, this is the name in the paramset statement. Otherwise, it could be the name of a "subckt", "model", or a standard device. This is called "master" in the Spectre manual. | * **Type** : The type of component. If there is a "paramset" statement, this is the name in the paramset statement. Otherwise, it could be the name of a "subckt", "model", or a standard device. This is called "master" in the Spectre manual. | ||
| - | * **Arguments** : A list of arguments (parameters or values). All arguments are name - value pairs, of the form ".name(value)", separated by a comma. The value may be an expression. In some cases, a principal value can be given just by value, without its name. The argument list is surrounded by parentheses, and prefixed by "#". | + | * **Parameters** : A list of parameters. All parameters are name - value pairs, of the form ".name(value)", separated by a comma. The value may be an expression. In some cases, a principal value can be given just by value, without its name. The parameter list is surrounded by parentheses, and prefixed by "#". |
| * **Label** : a string. The first letter has no significance. | * **Label** : a string. The first letter has no significance. | ||
| - | * **Port list** : A list of the ports (connections), separated by a comma. Mapping can be determined by order or by name. The port list should be surrounded by parentheses. By order, list them, comma separated. By name, they use the same syntax as arguments. .name(value) | + | * **Port list** : A list of the ports (connections), separated by a comma. Mapping can be determined by order or by name. The port list should be surrounded by parentheses. By order, list them, comma separated. By name, they use the same syntax as parameters. .name(value) |
| - | resistor #(10K) Rload (out, 0); // one unnamed argument, ports by order | + | resistor #(10K) Rload (out, 0); // one unnamed parameter, ports by order |
| - | resistor #(.r(10K)) Rload (.p(out), .n(0)); // the same component, arguments by name, ports by name | + | resistor #(.r(10K)) Rload (.p(out), .n(0)); // the same component, parameters by name, ports by name |
| amp #(.rload(100K)) X1 (.out(out), .in(in), .vcc(vc)); | amp #(.rload(100K)) X1 (.out(out), .in(in), .vcc(vc)); | ||
| Line 54: | Line 54: | ||
| // Now it is back in Verilog mode. | // Now it is back in Verilog mode. | ||
| + | In addition to this, "attributes" are supported. Attributes store meta-data that may be used by some other application, or in special cases. Attributes are attached to something, like the instance, a parameter, or port. Attributes are name=value pairs, or just names. | ||
| + | (* type=wirelead, rating="1/4 watt" *) resistor #((* color=red *).r(10K)) Rload ((* up *) out, 0); | ||
| ====== Top-level blocks ====== | ====== Top-level blocks ====== | ||
| Line 63: | Line 65: | ||
| ==== new/WIP ==== | ==== new/WIP ==== | ||
| - | This relates to task 2a in [[gnucap::nlnet22]]. | + | This relates to task 2a in [[gnucap:projects:nlnet:verilogams]]. The following is implemented in the modelgen-verilog package and bundled with the device plugins ("mgsim") therein. See the examples directory in gnucap-modelgen-verilog for various live applications. |
| A "paramset" statement creates a new type from an existing type. It becomes a "master" that can be instantiated later. It is similar to a spice ".model". | A "paramset" statement creates a new type from an existing type. It becomes a "master" that can be instantiated later. It is similar to a spice ".model". | ||
| Line 93: | Line 95: | ||
| paramset thingy resistor; | paramset thingy resistor; | ||
| - | parameter R; | + | parameter real R; |
| .r = R; | .r = R; | ||
| endparamset | endparamset | ||
| paramset thingy vsource; | paramset thingy vsource; | ||
| - | parameter V; | + | parameter real V; |
| .dc = V; | .dc = V; | ||
| endparamset | endparamset | ||
| Line 106: | Line 108: | ||
| endmodule | endmodule | ||
| + | Another criterion is parameter ranges. | ||
| + | |||
| + | paramset nfet some_nfet; | ||
| + | parameter level=1 from [1:1]; | ||
| + | [..] | ||
| + | endparamset | ||
| + | paramset nfet some_other_nfet; | ||
| + | parameter level=2 from [2:2]; | ||
| + | [..] | ||
| + | endparamset | ||
| + | |||
| + | module example2(1, 2) | ||
| + | nfet #(.level(1)) n1(1, 2, 3, 4); // is some_nfet | ||
| + | nfet #(.level(2)) n1(1, 2, 3, 4); // is some_other_nfet | ||
| + | endmodule | ||
| + | |||
| + | Another one is port names. If port names are used in the instantiation, a matching prototype is required. | ||
| + | Another criterion is number of parameters. If two prototypes match, the one with fewer parameters wins. This can be used to optimise out unwanted functionality and overhead. | ||
| + | |||
| + | module example3(1, 2) | ||
| + | capacitor #(.c(1), .ic(1)) c1(1, 2); // pick a model that has initial conditions | ||
| + | capacitor #(.c(1)) c2(1, 2); // avoid the overhead | ||
| + | resistor #(.r(1), .tc1(42.), tc2(17.)) r1(1, 2); // pick a model that has temperature dependency | ||
| + | resistor #(.r(1)) r2(1, 2); // avoid the overhead | ||
| + | endmodule | ||
| ==== current ==== | ==== current ==== | ||
| - | (This will be deleted once the above is ready.) | + | This description applies to the default plugin included with the Gnucap package, as of August 2023. |
| A "paramset" statement sets parameters based on an existing compiled model. This will be extended to cover all "masters". It becomes a "master" that can be instantiated later. It is equivalent to a spice ".model". | A "paramset" statement sets parameters based on an existing compiled model. This will be extended to cover all "masters". It becomes a "master" that can be instantiated later. It is equivalent to a spice ".model". | ||
| Line 161: | Line 188: | ||
| resistor #(.r(rload))Rload(out, 0 ); | resistor #(.r(rload))Rload(out, 0 ); | ||
| endmodule | endmodule | ||
| + | |||
| + | The following segment shows how the above ''amp'' module might be instantiated. | ||
| amp #(.rload(100K)) X1 (.out(out), .in(in), .vcc(vc)); | amp #(.rload(100K)) X1 (.out(out), .in(in), .vcc(vc)); | ||
| Line 166: | Line 195: | ||
| vsource #(.ac(1)) Vin (.p(in), .n(0)); | vsource #(.ac(1)) Vin (.p(in), .n(0)); | ||
| resistor #(10K) Rload (out, 0); | resistor #(10K) Rload (out, 0); | ||
| + | |||
| + | Attributes are supported. Usually they are just stored for the purpose of interoperation with other software. | ||
| + | |||
| + | (* structural *) module amp (out, in, (* optional *) vcc); | ||
| + | (* show *) parameter rload=10K; | ||
| + | .... | ||
| ====== Commands ====== | ====== Commands ====== | ||