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gnucap:manual:languages:verilog [2026/04/29 10:11] felixs overloading: tie break rules |
gnucap:manual:languages:verilog [2026/05/12 06:40] (current) felixs Update, clarifications |
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| verilog | verilog | ||
| - | ====== Components ====== | + | ====== Component instances ====== |
| - | All components have the same syntax: | + | All component instances have the same syntax: |
| type #(parameters) label (port list) ; | type #(parameters) label (port list) ; | ||
| Line 68: | Line 68: | ||
| Unlike Verilog, Gnucap allows device instances at top level, in addition to "paramset" and "model" declarations. | Unlike Verilog, Gnucap allows device instances at top level, in addition to "paramset" and "model" declarations. | ||
| Right now (Feb 2026), uninstanciated modules do **not** turn into instances automatically. They need to be instanciated explicitly. | Right now (Feb 2026), uninstanciated modules do **not** turn into instances automatically. They need to be instanciated explicitly. | ||
| + | |||
| + | This means, a top level module like | ||
| + | |||
| + | module main(); | ||
| + | [..] | ||
| + | endmodule; | ||
| + | |||
| + | must be followed by a line similar to | ||
| + | |||
| + | main #() mymain(); | ||
| + | |||
| + | to get the full effect. As of May '26 this restriction does no longer apply to process parameter containers, such as | ||
| + | |||
| + | module myprocess(); | ||
| + | localparam real toxify=42.; | ||
| + | endmodule | ||
| + | |||
| + | eg, $root.myprocess.toxify may be accessed from a behavioural model (compiled with Modelgen-Verilog). | ||
| ===== paramset ===== | ===== paramset ===== | ||
| Line 223: | Line 241: | ||
| (* show *) parameter rload=10K; | (* show *) parameter rload=10K; | ||
| .... | .... | ||
| + | |||
| + | ====== Behavioural models ====== | ||
| + | |||
| + | In addition to a plain netlists a 'module' may also contain behavioural modelling structures like variables, analog blocks, assignment statements. These are not directly understood by the simulator, but need to be processed/compiled and then loaded as device plugins. | ||
| + | For this purpose, we provide Modelgen-Verilog. | ||
| ====== Commands ====== | ====== Commands ====== | ||
| Line 228: | Line 251: | ||
| The Verilog language has no concept of commands. | The Verilog language has no concept of commands. | ||
| - | In gnucap, commands are executed at top level the same as the native mode. | + | In Gnucap, commands are executed at top level the same as the native mode. |
| ====== Extras ====== | ====== Extras ====== | ||
| Line 245: | Line 268: | ||
| This step will become unnecessary at some point in the future. Remaining caveats (Feb 2026) are | This step will become unnecessary at some point in the future. Remaining caveats (Feb 2026) are | ||
| - | * The devices and commands are whatever gnucap has installed, not necessarily what is defined in any standard. | + | * The devices and commands are whatever Gnucap has installed, not necessarily what is defined in any standard. |
| - | * The circuit must be defined before any commands using it, unless you want to simulate a partial circuit. Scripted and interactive modifications to the circuit are done the way gnucap usually does. | + | * The circuit must be defined before any commands using it, unless you want to simulate a partial circuit. Scripted and interactive modifications to the circuit are done the way Gnucap usually does. |
| * The main circuit can also be in Verilog syntax. The Verilog standard has no concept of components at top level. | * The main circuit can also be in Verilog syntax. The Verilog standard has no concept of components at top level. | ||
| * To simulate, there must be a component at top level. Uninstantiated modules do nothing. | * To simulate, there must be a component at top level. Uninstantiated modules do nothing. | ||
| - | * Overloading does not fully work at top level. | + | * Overloading did not fully work for top level instances before May '26. |
| * Discipline statements like "electrical" are not supported and/or do nothing yet. | * Discipline statements like "electrical" are not supported and/or do nothing yet. | ||