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gnucap:manual:tech:spice2verilog [2025/07/07 08:56] felixs fix example model code |
gnucap:manual:tech:spice2verilog [2025/09/02 06:52] (current) felixs add reference to inverse |
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| Verilog-AMS has been designed to coexist with Spice, and to replace it as needed (among other things). Citing from Annex E of the language reference manual, //Analog simulation has long been performed with SPICE and SPICE-like simulators. As such, there is a huge legacy of SPICE netlists.// These are supposed to retain its use when upgrading a SPICE simulator. On the other hand, Annex E provides a list of "SPICE primitives" that facilitate the rewrite of basic SPICE netlists. | Verilog-AMS has been designed to coexist with Spice, and to replace it as needed (among other things). Citing from Annex E of the language reference manual, //Analog simulation has long been performed with SPICE and SPICE-like simulators. As such, there is a huge legacy of SPICE netlists.// These are supposed to retain its use when upgrading a SPICE simulator. On the other hand, Annex E provides a list of "SPICE primitives" that facilitate the rewrite of basic SPICE netlists. | ||
| + | (See [[gnucap:manual:tech:verilog2spice|Using Verilog circuits in a SPICE-only simulator]] for a solution of the inverse problem.) | ||
| ==== SPICE Subsystem ==== | ==== SPICE Subsystem ==== | ||