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gnucap:manual:tech:verilog [2025/05/11 14:35] felixs hierarchy |
gnucap:manual:tech:verilog [2025/05/19 16:18] (current) felixs typo |
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Using modelgen-verilog (and gcc) we turn behavioural models into device plugins for use | Using modelgen-verilog (and gcc) we turn behavioural models into device plugins for use | ||
in the simulator with implementation notes [[.modelgen|here]]. The following sections relate to the structural subset, and its implementation | in the simulator with implementation notes [[.modelgen|here]]. The following sections relate to the structural subset, and its implementation | ||
- | on the simulator side implementation on the simulator side. | + | on the simulator side. |
==== module ==== | ==== module ==== |