gnucap:projects:nlnet:verilogams [*]

This is an old revision of the document!

In late '22, we have secured some funding from the NLnet Foundation alowing us to work on Verilog-AMS support. Within the next months, we will work on two tasks. One task is a compiler for behavioural models, the other is Verilog support on the simulator level.

Each task has 8 milestones. Here we will give details and keep track of our progress.

Task 1. modelgen-verilog: Provide a replacement for ADMS

a) Implement Verilog-AMS style branches and contributions

Branches and Contributions are explained here. The implementation is part of the develop branch as of March 5.

b) Generate partial derivatives of expressions, needed by Newton's method

How to evaluate partial derivatives. An implementation is ready here. This Task is complete.

c) Snapshot release supporting minimalistic devices with test suite.

d) Support for loops, conditionals and built-ins as plugins.

e) Add specific commonly used language features, ddt, idt.

The ddt and idt operators are part of the develop branch as of May 4.

f) Include test cases from the LRM and the Designers Guide.

g) Write user documentation and technical notes.

h) Set up examples involving common third party compact models.

Task 2. Verilog-AMS compliance on the simulator level

a) Model overloading by name and parameter ranges according to standard.

Verilog defines “paramset” as a means to replace model cards known from spice, cf. LRM section 6.4. The standard essentially allows multiple prototypes by the same name with mutually different interfaces (see usage), allowing things like recursive models. This requires changes to the way device instances are read in and elaborated read in and elaborated. Preliminary code is available here. Some of it has been added to Gnucsator.

b) Implement preprocessor, support backtick, macros, conditionals.

Slightly deviating from the workplan, we have added Preprocessing for compiler directives directly to the model compiler. The code is available here and combines preprocessing with evaluating derivatives (Task 1b).

c) Add support for "attribute instance".

d) Provide logic gates as plug-ins, accessible from Verilog netlists.

e) Integrate "model card" hierarchy into Verilog language semantics.

To be able to use models implemented for Spice in a Verilog environment, we need to be able to reference these models from paramset statements. Spice has both component letters and model identifiers, whereas Verilog only uses type names etc.. Spice hardwires the segmentation into shared and individual storage, while Verilog leaves it to the user. We may have to find a way to avoid performance regressions.

f) Refactor internals; make dc sweep work with parameters.

Historically, the dc sweep command only sweeps element values, following other implementations such as Spice 1-3 and Ngspice. We have redefined the data path for parameter values in devices, in particular “precalc_last” and edited simple devices (elements) accordingly. With these changes, we provide parameter sweeps in Gnucsator, mirroring Qucsator behaviour. We have refactored and adjusted the default dc command plugin and added support for parameter sweeps. Many new tests have been added in the process. This task is completed and part of the 20230214 snapshot.

g) Revisit build system: Improve model compilation and loading

Currently, Gnucap loads precompiled binary plugins. We will automate the compilation process for a better user experience, especially because Verilog-AMS behavioural code must be compiled prior to loading.