Differences

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--- gnucap:user:netlist_import_and_export [2024/08/15 22:01]
aldavis [Adding physical position]
+++ gnucap:user:netlist_import_and_export [2025/06/28 02:01] (current)
felixs fix reference to r2 (was: p2)
@@ Line 138: / Line 138: @@
   module amp (a, c);
-A "module" is the unit of encapsulation.  This one is called "amp", and it has two connections to outside, "a" and "c".
+A //module// is the unit of encapsulation.  This one is called ''amp'', and it has two connections to outside, ''a'' and ''c''.
   resistor #(.r(1k)) r1 (.p(a), .n(b));
-This line instantiates a "resistor".  It could be a symbol, a device, a footprint, depending on the application.
+This line instantiates a ''resistor''.  It could be a symbol, a device, a footprint, depending on the application.
-The "#" introduces a parameter list.  "r" is the name of a parameter.  "1k" is the value (a string).
+The ''#'' introduces a parameter list.  ''r'' is the name of a parameter.  ''1k'' is the value (a string).
-"r1" is the instance name,
+''r1'' is the instance name,
-It has two pins, named "p" and "n'.  Node "b" connects to pin "p" and node "c" connects to pin "n".
+It has two pins, named ''p'' and ''n''.  Node ''a'' connects to pin ''p'' and node ''b'' connects to pin ''n''.
-The type ("resistor") refers to a model in simulation.  In layout or schematic, it would refer to a footprint, indirectly.
+The type (''resistor'') refers to a model in simulation.  In layout or schematic, it would refer to a footprint, indirectly.
 In simulation, the models often come from some place external, or might come with the simulator.  You might substitute different models for the same device, depending what you want to do.
@@ Line 161: / Line 161: @@
   module amp (.a(a0), .c(c0));
+    ground gnd;
     resistor #(.r(1k)) r1 (.p(a1), .n(b1));
     resistor #(.r(1k)) r2 (.p(b2), .n(c2));
-    opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .pn(b3));
+    opamp741 #(.gain(100k)) u1 (.p(c3), .n(gnd), .ps(gnd), .pn(b3));
     net a (a0, a1);
@@ Line 172: / Line 173: @@
 We have replaced the nodes with nets, which are now first class objects.   This will give us a way to represent the interconnect in a schematic drawing or a layout.  It also provides essential data to support analysis and simulation of the interconnect.
-Looking at net "b" as an example, it has 3 connections : r1 pin n, p2 pin p, and u1 pin pn.
+Looking at net ''b'' as an example, it has 3 connections : ''r1'' pin ''n'', ''r2'' pin ''p'', and ''u1'' pin ''pn''.
 What is a "net"?  It depends how you look at it.  It could be the lines on a schematic, or the traces on a PC board.  If we are doing a Spice-type simulation, we would want to collapse it into a single node.  So we might define:
@@ Line 180: / Line 181: @@
 This definition gives us up to 6 connections (a,b,c,d,e,f) as seen from outside, all connected together internally, which has the effect of collapsing it all down to one.
+==== The "rail" device ====
+We use rail devices with a single port to make connections to designated circuit nodes, possibly across hierarchy. This removes the need for "global" nodes, which are known from Spice and prone to error.
+  module amp(.a(a0), .c(c0), .vdd(vdd));
+    [..]
+    electrical vdd; // rvv connects to here.
+    rail #(.node("vdd")) rvv(vv);
+    op #(.gain(100k)) u1 (.p(c3), .n(nn), .ps(b2), .pn(b3), .vdd(vv), .vss(nn1));
+    rail #(.node("gnd")) rg1(nn);
+    rail #(.node("gnd")) rg2(nn2);
+    net nn(nn1, nn2);
+    [..]
+  endmodule
+  module top();
+    ground gnd; // <= a0.rg1 and a0.rg2 connect to here.
+    amp a0(a, b, v);
+    [..]
+  endmodule
+A possible rail implementation may look like this
+  module rail(n);
+    electrical n;
+    parameter string node = "(nothing)";
+    analog initial begin
+      if(!$analog_node_alias(n, node))
+         $error("dangling rail, cannot find %s\n", node);
+    end
+  endmodule
+The rail connects to the node of the given name found by upwards traversal through the hierarchy. In particular, a rail does not create a node.
 ==== Verilog "system" parameters ====
-The Verilog standard defines some "system" parameters for all devices to show position.
+The Verilog standard defines some "hierarchical system parameters" (HSP) for all devices to show position.
   * $xposition (x coordinate, in meters)
@@ Line 190: / Line 225: @@
   * $vflip (flag: flip vertically, +1=no flip, -1=flip)
-These "system" parameters are real parameters, so we won't use them here.  We will use them as inspiration for "attributes" instead.
+These HSPs are real parameters, i.e. carry a physical meaning. Hence we will not use them to store schematic markup. We will use them as inspiration for positioning "attributes" instead.
+HSPs will generally be treated as ordinary parameters, but are subject to special semantics that attributes are not meant to carry. For backwards compatibility, all parameters with a name starting with '$' must be passed on like attributes and without interpretation where they have no meaning.
+The current standard misses out on HSPs that correspond to global options in legacy tools. In the future, HSPs such as $temperature, $dtemp, $method or $mode should be supported to localise such global options as required, but without workarounds.
 ==== Verilog "attributes" ====
-The Verilog standard gives a way to add "attributes" to just about anything.
+The Verilog standard gives a way to add "attributes" to just about anything. We are referring to
+//a mechanism [..] included for specifying properties about objects, statements and groups of statements in the HDL
+source that can be used by various tools// in IEEE1364 Section 3.8.
   (* attribute = value *) resistor r1 (.p(2), .n(3));
@@ Line 209: / Line 249: @@
 ==== Adding physical position ====
-Now we use the attributes to specify the location.  We need to locate the various objects.  In most cases, we need to specify some point of every object that will identify its location.  Some programs use some notion of a "center", which is ambiguous.  We will use the electrical connection points, often called "pins", as the location points for things that have an electrical connection.  For objects that do not have electrical connections, reference points can be used.
+Now we use the attributes to specify the location.  We need to locate the various objects in a suitable [[gnucap:user:schematic_geometry|coordinate system]]. In most cases, we need to specify some point of every object that will identify its location.  Some programs use some notion of a "center", which is ambiguous.  We will use the electrical connection points, often called "pins", as the location points for things that have an electrical connection.  For objects that do not have electrical connections, reference points can be used.
 We will number the pins, by position, 1, 2, ...  Then we use x1,y1, and so on to locate them.  Usually one of them is adequate to locate an object.  The others can "float", allowing the actual location to be determined by the surroundings.  It is permissible to overspecify locations, provided they are self-consistent, and consistent with connections.
@@ Line 334: / Line 374: @@
   (* S0_geda_symbol="resistor2.sym" *) resistor #(10k) r4 (a,b);
+==== Non-circuit items ====
+In addition to this, nearly all schematics have text or drawings that are not part of the circuit.  In this case we use dummy devices, with type name beginning with an ''S''''_''''_'' prefix. For text, the position is the point where the base line begins.
+  (* S0_x=1.5u, S0_y=1.5u, S0_text="This is some text" *) S__text text42();
+Generic application dependent graphics objects should be represented by objects of type ''S_''''_graphics'', with attributes as required by a specific application, and optionally, ''S0_x/y'' attributes to indicate a ballpark position.
+  (* S0_x=4.5u, S0_y=5.5u, mytool_shape="triangle", more_attributes=[..] *) S__graphics t1();
+In order to ignore such objects in a simulator or similar context, declarations such as
+  module S__text();
+  endmodule;
+  module S__graphics();
+  endmodule;
+are required within the corresponding device library.
+==== PC boards ====
+PC boards are similar to schematics, with some additional features, and possibly different interpretation.
+On a schematic, a "net" is just connections, and objects in the schematic directly map to devices.  On a PC board, it can start at that, which enables basic simulation and bi-directional conversion between board and schematic.  When simulating a PC board, there are many ways to do that, and other types of models are often substituted.
+The meaning of a "net" could be:
+  * A connection, like a schematic.  Its connections are collapsed.
+  * A transmission line.  It then could have parameters, usually that would be a trace width and layer identifier.  It could easily map to a transmission line model, with attributes that could be used to extract data for signal integrity modeling.
+  * A delay.  Delays can be calculated from length.
+The symbols on a schematic map to footprints on a layout.  They could be the same, or could substitute alternate models for signal integrity, such as IBIS models.  This is one reason that it is best that the Verilog type should not be exactly a simulation model, but rather something that can be mapped by a paramset, with different models for different uses.
+A layout needs to add **stackup** information, which would be attributes of the enclosing **module**.
+==== Chip layout ====
+This method could apply to chip layout too, but requires more study, because the symbol/footprint concept is not used in chip layout, and what you can do is more tied to process specifics.
+==== Examples ====
+ - [[gnucap:user:netlist_import_and_export:geda|gEDA/Lepton schematics]]
+ - [[gnucap:user:netlist_import_and_export:qucs|Qucs (reworked) schematics]]