In late '22, we have secured some funding from the NLnet Foundation alowing us to work on Verilog-AMS support. Within the next months, we will work on two tasks. One task is a compiler for behavioural models, the other is Verilog support on the simulator level.
Each task has 8 milestones. Here we will give details and keep track of our progress.
Verilog defines “paramset” as a means to replace model cards known from spice, cf. LRM section 6.4. The standard essentially allows multiple prototypes by the same name with mutually different interfaces usage. This requires changes to the way device instances are read in and elaborated TODO_IMPL.
Historically the dc sweep command only sweeps elements. Currently, in Gnucap sweeping parameters is more tedious than in other simulators. We will adjust and redefine the data path for parameter values TODO_IMPL, and extend the dc command plugin to make use of it.
To be able to use models implemented for Spice in a Verilog environment, we need to be able to reference these models from paramset statements. Spice has both component letters and model identifiers, whereas Verilog only uses type names etc.. Spice hardwires the segmentation into shared and individual storage, while Verilog leaves it to the user. We may have to find a way to avoid performance regressions.
Currently, Gnucap loads precompiled binary plugins. We will automate the compilation process for a better user experience, especially because Verilog-AMS behavioural code must be compiled prior to loading.